AN1810/0305 1/8 rev. 2.0 AN1810 application note str71x bspi communication with m25p10-a serial flash introduction the aim of this application note is to prese nt a practical example of communication using the bspi peripheral of the str71x. it shows an easy way of communicating between a str71x microcontroller and a m25p10-a spi serial flash memory. the purpose is to perform, through bspi, a write in the memory, followed by a read of the written data. the software implemented manages write and read operations between the str71x bspi- interface and the m25p10-a serial flash memory from stmicroelectronics. 1 application overview this section summarizes the main features of the connection between str71x and the spi flash memory. the buffered serial peripheral interface (bspi ) allows full-duplex, synchronous, serial com- munication between devices. a bspi system may co nsist of a master and several slaves, or of a system in which devices may be either master or slave. there is only one master at any time. during bspi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). data is transmitted msb first. the serial clock is used to synchronize the data transfer during a sequence of eight clock pulses. the bus signals are: ? the serial clock (sclk). ? the mosi (master out slave in). ? the miso (master in slave out). another pin, the ssn pin (slave select), is needed to select slave or master mode for each device. in this application note, the str71x is always used as master (s1.ssn pin = high level). the str71x and spi flash interface set-up is shown in figure 2. 1
2/8 str71x bspi communication with m25p10-a serial flash 2 str71x configuration 2.1 i/o control five pins of the str71x are used: ? the 4 (data and clock) bspi pins (s1.sclk, s1.mosi, s1.miso, s1.ssn) ? an output (p0.3) pin to select and deselect the m25p10-a in this application, the p0.3 pin is used to driv e the m25p10-a chip select pin. it is configured as output push-pull (refer to the str71x reference manual for more details). 2.2 bspi peripheral 2.2.1 baud rates firstly, you have to choose the bspi communication speed. as the clock is given by the mas- ter, you must configure the baud rate of the str71x using the function bspi_clockdividerconfig(bspi1,divider_factor_bits) or directly with the bspi1_clk register (refer to str71x reference manual for more details). note : in master mode, the divider_factor_bits parameter must be an even number greater than five (refer to str71x reference manual for more details). 2.2.2 clock phase and polarity the next items to configure are the clock polarity and phase. the clock polarity cpol con- trols the steady state value of the clock when no data is being transferred. the clock phase cpha selects on which clock transition the bit capture is made and conse- quently on which clock transition data is latched. you must be careful because some devices do not allow all timing relationships. for instance, the m25p10-a serial flash memory device ac cepts only cpol,cpha = (0,0) or (1,1) config- urations. 2
3/8 str71x bspi communication with m25p10-a serial flash 3 m25p10-a serial flash memory management and configuration 3.1 summary description the m25p10-a is a 1 mbit (128k * 8) seri al flash memory, with advanced write protection mechanisms, accessed by a high speed spi -compatible bus. the memory can be pro- grammed 1 to 256 bytes at a time, using the page program instruction. the write protect pin (w ) and the hold pin (h ) are not used in our application (both are high level). 3.2 status register the device has one status register which contains a number of control bits and status bits, as shown in the following figure: figure 1. status register control and status bits the srwd bit is operated in conjunction with the write protect (w ) signal. the bp1 and bp0 bits in the status register can be used to write protect a block of memory. in this application, both bits are cleared, allowing write access to all memory. the wel bit indicates the status of the write enable latch. the wip bit indicates whether the memory is busy with a write status register, program or erase cycle. 3.3 instruction set prior to any operation, the device must be selected (s pin at low level), then a one-byte instruction code must be sent to the serial flash memory. the device has a set of 11 instruc- tions: (see table 1, ?instruction set,? on page 4). 00 0bp1 srwd bp0 wel wip status register write protect write enable latch bit write in progress bit block protect bit
4/8 str71x bspi communication with m25p10-a serial flash table 1. instruction set instruction description one-byte in- struction code address bytes dummy bytes data bytes wren write enable 0000 0110 000 wrdi write disable 0000 0100 000 rdsr read status register 0000 0101 001 to wrsr write status register 0000 0001 001 read read data bytes 0000 0011 301 to fast_read read data bytes at higher speed 0000 1011 311 to pp page program 0000 0010 3 0 1 to 256 se sector erase 1101 1000 300 be bulk erase 1100 0111 000 dp deep power-down 1011 1001 000 res release from deep power-down, and read electronic signature 10101011 031 to release from deep power-down 000
5/8 str71x bspi communication with m25p10-a serial flash 4 communication between str 71x and serial flash memory the software included with this application note offers a set of functions allowing communica- tion with the flash memory. the complete software can be found on the st internet website. it is a particular example and it is up to you to adapt it to your specific application. 4.1 hardware description two components were used for the application: ? 1 str71x mcu device. ? 1 m25p10-a serial flash memory figure 2. hardware overview s1.ssn pin of str71x is hardware driven (high level for a master device). the s1.sclk pin is connected to the serial clock pin (c) of the serial flash memory. the s1.mosi pin to the serial input pins (d). the s1.miso pin to the serial output pins (q). s pin of the serial flash memory is connected to the p0.3 output pin of the str71x. 4.2 software implementation in this application note the software modules are developed in c language, with rvdk envi- ronment. the software implemented in order to manage write and read operations between the str71x bspi interface and the m25p10-a is described below. it is made up of 4 parts: s q w d h s1.ssn s1.sclk s1.miso s1.mosi p0.3 1 cc v c v ss v ss cc v m25p10-a c 100nf cc v cc v str71x 10k
6/8 str71x bspi communication with m25p10-a serial flash 1) configuration of bspi1 as a master, 2) erase m25 spi flash sector0, 3) transmission of several bytes from master to m25 spi flash, 4) read data already written to the m25 spi flash. 4.2.1 flowchart the flowchart of the application is given below. begin /* send read status register instruction */ m25_instructionsend(m25_rdsr); /* wait until all the sector is erased */ while((m25_datareceive()&m25_wip)); /* initialize str71x bspi device */ initbspiflash (); chip_select_m25_disable; chip_select_m25_enable; read status register chip select pin driven high / low send a write enable instruction /* send a write enable instruction to the memory */ m25_instructionsend(m25_wren); memory sector0 erase /* erase sector0 from the memory */ m25_sectorerase(m25_sector0); initialization { ... /* send a write enable instruction to the memory */ m25_instructionsend(m25_wren); send a write enable instruction verify that all the data sent is programmed /* send read status register instruction */ m25_instructionsend(m25_rdsr); /* wait until all the data sent is programmed */ while((m25_datareceive()&m25_wip)); /* send page program instruction */ m25_instructionsend(m25_pp); /* wait until all the data is sent */ for (i=0;i 7/8 str71x bspi communication with m25p10-a serial flash send instruction in order to read data from the memory /* send a read data byte instruction */ m25_instructionsend(m25_read); send address memory to be read /* send address memory to be read */ m25_addresssend(m25_readaddress); verify that all the data is read /* read all the data already written */ for (i=0;i 8/8 str71x bspi communication with m25p10-a serial flash ?the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connection with their products.? information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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